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AN30259C product standards page 1 of 33 typical application features description 3-ch. led driver for illumination an30259a has 3-ch. led driver, suitable for rgb illumination. by synchronous clock function, simultaneous led turn on/off operation of up to 4 ics can be achieved. ? i 2 c interface (slave address is switchable.) ? built-in 3-ch. led driver circuit ( max current selectable [63.75 ma / 31.875 ma / 25.50 ma / 12.75 ma] ) ? 2.4 mhz osc ? 12 pin wafer level chip size package (wlcsp) top view applications led 39 k ? c1 sda c2 scl b1 ad sel2 b2 ad sel1 b3 gnd a1 iref a3 clk pwm c3 vdd a2 vcc b4 led2 a4 led3 c4 led1 i 2 c interface clk input 1 ? f 10 ? f http://www.semicon. panasonic.co.jp/en/ ? mobile phone ? smart phone ? pcs ? game consoles ? home appliances etc. note) this application circuit is an example. the operation of the mass production set is not guaranteed. customers shall perform enough evaluation and verification on the design of mass production set. customers shall be fully responsible for the incorpora tion of the above application circuit and information in the design of the equipment. d o c n o . t a4 - ea - 06119 r e v i sio n . 2 e s t a b li s h e d : 2012 - 09 - 18 r e v i s e d : 2013 - 02 - 09
AN30259C product standards page 2 of 33 absolute maximum ratings *2 ? c ?30 to + 85 t opr operating ambience temperature *2 ? c ? 30 to + 125 t j operating junction temperature *2 ? c ?55to+125 t stg storage temperature ? v ? 0.3 to 4.3 adsel1, adsel2, scl, sda, clkpwm input voltage range output voltage range ? v ? 0.3 to 6.5 led1, led2, led3 ? kv 2.0 hbm (human body model) esd *1 v 4.6 vdd max note unit rating symbol parameter *1 v 7.0 vcc max supply voltage power dissipation rating note) for the actual usage, please refer to the p d -ta characteristics diagram in the package specification, supply voltage, load and ambient temperature conditions to ensure that there is enough margin follow the power and the thermal design does not exceed the allowable value. caution note) this product may sustain permanent damage if subjected to conditions higher than the above stated absolute maximum rating. this rating is the maximum rating and device operating at this range is not guaranteeable as it is higher than our stated recommended operating range. when subjected under the absolute maximum rating for a long time, the reliability of the product may be affected. * 1: vcc max = vcc, vdd max = vdd, the values under the condition not exceeding the above absolute maximum ratings and the power dissipation. *2: except for operating ambient temperature, operating junction temperature and storage temperature, all ratings are for t a = 25 ? c. 0.074 w 0.186 w 537.1 ? c /w 12 pin wafer level chip size package (wlcsp) p d (ta=85 ? c) p d (ta=25 ? c) ? ja package although this ic has built -in esd protection circuit, it may st ill sustain permanent damage if not handled properly. therefore, proper esd precautions are recommended to avoid electrostatic damage to the mos gates d o c n o . t a4 - ea - 06119 r e v i sio n . 2 e s t a b li s h e d : 2012 - 09 - 18 r e v i s e d : 2013 - 02 - 09
AN30259C product standards page 3 of 33 recommended operating conditions *1 v vdd + 0.3 ? ?0.3 adsel1, adsel2, scl, sda, clkpwm input voltage range output voltage range *1 v vcc + 0.3 ? ?0.3 led1, led2, led3 ? v 6.0 3.7 3.1 vcc 1.85 typ. 1.7 min. ? v 3.2 vdd supply voltage range note unit max. symbol parameter note) voltage values, unless otherwise specified, are with respect to gnd. gnd is voltage for gnd. vdd is voltage for vdd. vcc is voltage for vcc. *1 : ( vdd + 0.3 ) v must not be exceeded 4.6 v. ( vcc + 0.3 ) v must not be exceeded 7 v. d o c n o . t a4 - ea - 06119 r e v i sio n . 2 e s t a b li s h e d : 2012 - 09 - 18 r e v i s e d : 2013 - 02 - 09
AN30259C product standards page 4 of 33 ? v 0.4 0.2 ? imax[1:0] = 01, terminal minimum voltage of led1 to 3 becoming 85% of the led current value in 1 v. v sat minimum voltage for retainable constant current value 5 0.18 27.54 0.864 0.15 1.0 ? ? ma 0.10 0.05 imax[1:0] = 01, v led1 to 3 =1.0v i min1 minimum setting current value 1 ? ma 0.80 0.736 imax[1:0] = 01, v led1 to 3 =1.0v i min2 minimum setting current value 2 ? ma 25.50 23.46 imax[1:0] = 01, v led1 to 3 =1.0v i max maximum setting current value ? ma 0.10 0.00 imax[1:0] = 01, v led1 to 3 =1.0v i step current step ? % ? ?5 12.80 ma setting, v led1 to 3 =1.0v i match error between channels internal oscillator mhz 2.88 2.40 1.92 ? f osc oscillation frequency ? ? a 5 1 ? v dd =1.8v i cc2 current consumption 2 off mode ? ma 1.0 0.6 ? i led1 to 3 = 25.50 ma setting all led = on i cc3 current consumption 3 led lighting mode ? ? a ? ? off setting v led1 to 3 =6.0v i leak off time leak current led driver current consumption ? ? a 2 0 ? v dd =0v i cc1 current consumption 1 off mode limits typ unit max note min condition symbol parameter electrical characteristics v cc = 3.6 v, v dd = 1.8 v note) t a = 25 ? c ? 2 ? c unless otherwise specified. d o c n o . t a4 - ea - 06119 r e v i sio n . 2 e s t a b li s h e d : 2012 - 09 - 18 r e v i s e d : 2013 - 02 - 09
AN30259C product standards page 5 of 33 electrical characteristics (c ontinued) v cc = 3.6 v, v dd = 1.8 v note) t a = 25 ? c ? 2 ? c unless otherwise specified. ? v v dd + 0.2 ? v dd ? 0.7 ? v ih3 high-level input voltage range ? v v dd ? 0.3 ? ?0.2 ? v il3 low-level input voltage range ? ? a 1 0 ? v adsel1, 2 = 1.8 v i ih3 high-level input current ? ? a 1 0 ? v adsel1, 2 = 0 v i il3 low-level input current ? ? a 1 0 ? v sda ,v scl = 0 v i il1 low-level input current ? ? a 1 0 ? v sda ,v scl = 1.8 v i ih1 high-level input current *1 v v dd ? 0.3 ? ?0.5 voltage which recognized that sda and scl are low-level v il1 low-level input voltage range *1 v v dd + 0.5 ? v dd ? 0.7 voltage which recognized that sda and scl are high-level v ih1 high-level input voltage range ? v v dd ? 0.3 ? ?0.2 ? v il2 low-level input voltage range ? m ? 2.0 1.0 0.5 ? r pd2 pin pull down resistance value ? v v dd + 0.2 ? v dd ? 0.8 i clkpwm = ? 2 ma v oh2 high-level output voltage ? v v dd ? 0.2 ? ?0.2 i clkpwm = 2 ma v ol2 low-level output voltage adsel1, adsel2 ? v 0.2 ? v dd ? 0 i sda = 3 ma, v dd < 2 v v ol1l low-level output voltage2 (sda) ? khz 400 ? 0 ? f scl scl clock frequency ? v v dd + 0.2 ? v dd ? 0.7 ? v ih2 high-level input voltage range clkpwm scl, sda ? v 0.4 ? 0 i sda = 3 ma, v dd > 2 v v ol1h low-level output voltage1 (sda) limits typ unit max note min condition symbol parameter note)*1: the input threshold voltage of i 2 c bus (vth) is linked to v dd (i 2 c bus i/o stage supply voltage). in case the pull-up voltage is not v dd , the threshold voltage (vth) is fixed to ((v dd / 2) ? (schmitt width) / 2 ) and high-level, low-level of input voltage are not specified. in this case, pay attention to low-level (max.) value (v ilmax ). it is recommended that the pull-up voltage of i 2 c bus is set to the i 2 c bus i/o stage supply voltage (v dd ). d o c n o . t a4 - ea - 06119 r e v i sio n . 2 e s t a b li s h e d : 2012 - 09 - 18 r e v i s e d : 2013 - 02 - 09
AN30259C product standards page 6 of 33 max typ note unit limits condition symbol parameter min clkpwm *2 ? s ? 2.5 ? ? w pwm external pwm operation mode possible input high pulse width electrical characteristics (c ontinued) v cc = 3.6 v, v dd = 1.8 v note) t a = 25 ? c ? 2 ? c unless otherwise specified. note) *2 : typical design value d o c n o . t a4 - ea - 06119 r e v i sio n . 2 e s t a b li s h e d : 2012 - 09 - 18 r e v i s e d : 2013 - 02 - 09
AN30259C product standards page 7 of 33 max typ note unit limits condition symbol parameter min *3 v ? ? 0.05 ? v dd scl, sda hysteresis voltage vdd > 2 v v hys1 input voltage hysteresis (1) *3 v ? ? 0.1 ? v dd scl, sda hysteresis voltage vdd < 2 v v hys2 input voltage hysteresis (2) *3 ns 250 ? 20 + 0.1 ? c b bus capacitance : 10 pf to 400pf i p ? 6ma(v olmax = 0.6 v) i p : max. sink current t of output fall time from v ihmin to v ilmax *3 ns 50 ? 0 ? t sp spike pulse width kept down by input filter i 2 c bus (internal i/o st age characteristics) *3 pf 10 ? ? ? c i i/o pin capacitance electrical characteristics (c ontinued) v cc = 3.6 v, v dd = 1.8 v note) t a = 25 ? c ? 2 ? c unless otherwise specified. notes ) *3 these are values checked by design but not production tested. d o c n o . t a4 - ea - 06119 r e v i sio n . 2 e s t a b li s h e d : 2012 - 09 - 18 r e v i s e d : 2013 - 02 - 09
AN30259C product standards page 8 of 33 max typ note unit limits condition symbol parameter min *3,4 v ? ? 0.2 ? v dd ? v nh noise margin of each connection device at high-level *3,4 v ? ? 0.1 ? v dd ? v nl noise margin of each connection device at low-level *3,4 pf 400 ? ? ? c b capacitive load for each bus line *3,4 ? s ? ? 1.3 ? t buf bus free time between under "stop" condition and "start" condition *3,4 ? s ? ? 0.6 ? t su:sta recursive "start" condition setting time *3,4 ? s ? ? 0.6 ? t high scl clock "h" duration *3,4 ? s ? ? 1.3 ? t low scl clock "l" duration *3,4 ? s ? ? 0.6 after t hd:sta,. the first clock pulse is generated. t hd:sta hold duration (recursive) *3,4 ? s 0.9 ? 0 ? t hd:dat data hold time *3,4 ns ? ? 100 ? t su:dat data setup time *3,4 ns 300 ? 20 + 0.1 ? c b ? t r sda, scl signal rise up time *3,4 ns 300 ? 20 + 0.1 ? c b ? t f sda, scl signal fall time i 2 c bus (bus line specifications) *3,4 ? s ? ? 0.6 ? t su:sto setup time under "stop" condition scl sda t low t f t r t hd;sta t hd;dat t high t su;dat t f t su;sta t hd;sta t sp sr t su;sto t buf ps t r s s : start condition sr : repeat start condition p : stop condition electrical characteristics (c ontinued) v cc = 3.6 v, v dd = 1.8 v note) t a = 25 ? c ? 2 ? c unless otherwise specified. note) *3: these are values checked by design but not production tested. *4: the timing of fast-mode devices in i 2 c-bus is specified as follows. all values referred to v ihmin and v ilmax level. d o c n o . t a4 - ea - 06119 r e v i sio n . 2 e s t a b li s h e d : 2012 - 09 - 18 r e v i s e d : 2013 - 02 - 09
AN30259C product standards page 9 of 33 pin functions resistor connection pin for setting constant current value output iref a1 power supply pin for led circuit power supply vcc a2 reference clock input / output pin pwm signal input pin to control led brightness by the external pulse signal input/output clkpwm a3 led3 output pin output led3 a4 i 2 c interface slave address switch pin 2 input adsel2 b1 i 2 c interface slave address switch pin 1 input adsel1 b2 ground pin ground gnd b3 led2 output pin output led2 b4 i 2 c interface data input / output pin input/output sda c1 i 2 c interface clock input pin input scl c2 power supply pin for interface power supply vdd c3 led1 output pin output led1 c4 description type pin name pin no. pin configuration top view 1 2 3 4 c b a vcc iref clk pwm led3 gnd ad sel1 ad sel2 vdd scl sda led1 led2 d o c n o . t a4 - ea - 06119 r e v i sio n . 2 e s t a b li s h e d : 2012 - 09 - 18 r e v i s e d : 2013 - 02 - 09
AN30259C product standards page 10 of 33 functional block diagram note) this block diagram is for explaining functions. part of the block diagram may be omitted, or it may be simplified. waveform generator waveform generator waveform generator pwm pwm pwm current source current source current source vcc a2 b3 gnd iref a1 led1 c4 led2 b4 led3 a4 scl c2 sda c1 b2 adsel1 buffer osc vdd c3 clkpwm a3 i 2 c b1 adsel2 d o c n o . t a4 - ea - 06119 r e v i sio n . 2 e s t a b li s h e d : 2012 - 09 - 18 r e v i s e d : 2013 - 02 - 09
AN30259C product standards page 11 of 33 ? this lsi, i 2 c-bus, is designed to correspond to the standard-mode (100 kbps) and fast-mode(400 kbps) devices in the version 2.1 of nxp's specification. however, it does not correspond to the h s -mode (to 3.4 mbps). ? this lsi will be operated as a slave device in the i 2 c-bus system. this ic will not operate as a master device. ? the program operation check of this lsi has not be en conducted on the multi-master bus system and the mix-speed bus system, yet. the connect ed confirmation of this lsi to the cbus receiver also has not been checked. please confi rm with our company if it will be used in these mode systems. the i 2 c is the brand of nxp. 2) start and stop conditions a high to low transition on the sda line while scl is high is one such unique case. this situation indicates start condition. a low to high transition on the sda line while scl is high defines stop condition. start and stop conditions are always generated by the master. after start condition occurs, the bus will be busy. the bus is considered to be free again a certain time after the stop condition. every byte put on the sda line must be 8-bits long. the number of bytes that can be transmitted per transfer is unrestricted. each byte has to be followed by an acknowledge bit. data is transferred with the most significant bit (msb) first. operation 1. i 2 c-bus interface 1) basic rules 3) transferring data start condition stop condition sda scl acknowledgement signal from slave acknowledgement signal from receiver start or repeated start condition stop or repeated start condition scl sda msb ack ack 12 789 123 ?89 sr or p sr p s or sr d o c n o . t a4 - ea - 06119 r e v i sio n . 2 e s t a b li s h e d : 2012 - 09 - 18 r e v i s e d : 2013 - 02 - 09
AN30259C product standards page 12 of 33 read mode a) when sub-address is not assigned. b) when specifying sub-address when data is read without assigning sub-address, it is possible to read the value of sub-address specified in write mode immediately before. ex) when writing data into address and reading data from "01 h" slave address can be switched by adsel1, adsel2 pin connections. the chart on the right shows the slave address of this product. adsel1 low (ground) 30 h (0110000) low (ground) low (ground) 33 h (0110011) 32 h (0110010) 31 h (0110001) slave address high (vdd) low (ground) high (vdd) high (vdd) high (vdd) adsel2 s slave address a sub-address a data byte a p stop condition ack start condition w write mode : 0 write mode 7-bit 8-bit 8-bit s slave address a data byte a p stop condition ack start condition r read mode : 1 7-bit 8-bit s slave address a sub-address (01h) a data byte a p 0 s slave address a data byte a p 1 write read 7-bit 8-bit 8-bit 7-bit 8-bit s slave address a sub-address a data byte a p stop condition acknowledge bit start condition 0 write mode : 0 s slave address a repeated start condition 1 read mode : 1 ack ack sub-address should be assigned first. 7-bit 8-bit 7-bit 8-bit operation (continued) 1. i 2 c-bus interf ace (continued) 4) data format d o c n o . t a4 - ea - 06119 r e v i sio n . 2 e s t a b li s h e d : 2012 - 09 - 18 r e v i s e d : 2013 - 02 - 09
AN30259C product standards page 13 of 33 stop condition ack start condition write mode : 0 stop condition ack start condition read mode : 1 stop condition acknowledge bit start condition write mode : 0 repeated start condition read mode : 1 ack ack when the most significant bit specified in the last write mode is [1], it is possible to perform the continuous read mode operation directly after it. ex) case where data is read from address 01h after data is written to address 01h sub address is specified initially data byte slave address sub address slave address s ap a a 1 a 0 s data byte sub address slave address a p a a w s data byte slave address p a a r s data byte sub address 81h slave address a p a a 0 s ap data byte slave address data byte a a 1 s when using the continuous write mode, the most significant bit of sub address should be set to [1]. set most significant bit to [1]. ex) 05h ? 85h, 11h ? 91h set most significant bit to [1]. ? continuous write mode ? continuous read mode write read a) when sub address is not specified b) when sub address is specified 7-bit 8-bit 8-bit 7-bit 8-bit 7-bit 8-bit 8-bit 7-bit 8-bit 8-bit 7-bit 8-bit 7-bit 8-bit operation (continued) 1. i 2 c-bus interf ace (continued) 4) data format (continued) d o c n o . t a4 - ea - 06119 r e v i sio n . 2 e s t a b li s h e d : 2012 - 09 - 18 r e v i s e d : 2013 - 02 - 09
AN30259C product standards page 14 of 33 clkdir slp2dt1 [3:0] slp2dt2 [3:0] led2cnt3 r/w 0fh dutymin2 [3:0] delay2 [3:0] led2cnt2 r/w 0eh dutymid2 [3:0] dutymax2 [3:0] led2cnt1 r/w 0dh slp1dt3 [3:0] slp1dt4 [3:0] led1cnt4 r/w 0ch slp1dt1 [3:0] slp1dt2 [3:0] led1cnt3 r/w 0bh dlysel1 led1on sreset d0 slp3tt1 [3:0] slp3dt1 [3:0] slp3dt2 [3:0] led3cnt3 r/w 13h slp3dt3 [3:0] slp3dt4 [3:0] led3cnt4 r/w 14h slp2tt1 [3:0] slp2tt2 [3:0] led2slp r/w 07h slp1tt1 [3:0] slp1tt2 [3:0] led1slp r/w 06h led1cc [7:0] led1cc r/w 03h dutymid3 [3:0] dutymax3 [3:0] led3cnt1 r/w 11h dutymin1 [3:0] delay1 [3:0] led1cnt2 r/w 0ah dlysel2 dlysel3 extpwm ioen imax [1:0] sel r/w 02h led2cc [7:0] led2cc r/w ? ? slp2dt3 [3:0] slp2dt4 [3:0] led2cnt4 r/w 10h r/w r/w r/w r/w r/w w r/w dutymin3 [3:0] dutymid1 [3:0] delay3 [3:0] led3cnt2 12h led3cc [7:0] led3cc 05h 04h register name sub addr ess dutymax1 [3:0] led1cnt1 09h slp3tt2 [3:0] led3slp 08h led2on led3on ? led1md led2md led3md ? ledon 01h ? ? ? ? ? sreset 00h d5 d6 d7 data d1 d2 d3 d4 note) read value in " ?" is [0]. operation (continued) 2 register map d o c n o . t a4 - ea - 06119 r e v i sio n . 2 e s t a b li s h e d : 2012 - 09 - 18 r e v i s e d : 2013 - 02 - 09
AN30259C product standards page 15 of 33 d0 : software reset pin [0] : normal condition ( default ) [1] : reset (reset all the other register and returns to low automatically) 00 h r / w mode address 0 0 0 0 0 0 0 0 w default ? ? sreset ? ?? ? ? 00 h d5 d6 d7 sreset register name d0 d1 d2 d3 d4 operation (continued) 3 register map details d o c n o . t a4 - ea - 06119 r e v i sio n . 2 e s t a b li s h e d : 2012 - 09 - 18 r e v i s e d : 2013 - 02 - 09
AN30259C product standards page 16 of 33 00 h r / w mode address 0 0 0 0 0 0 0 0 r/w default led2md led3md led1on led3on led1md led2on ? ? 01 h d5 d6 d7 ledon register name d0 d1 d2 d3 d4 d6 : led3md led3 lighting mode setting [0] : led3 constant current mode ( default ) [1] : led3 slope mode d5 : led2md led2 lighting mode setting [0] : led2 constant current mode ( default ) [1] : led2 slope mode d4 : led1md led1 lighting mode setting [0] : led1 constant current mode ( default ) [1] : led1 slope mode d2 : led3on led3 enable control [0] : led3 off ( default ) [1] : led3 on d1 : led2on led2 enable control [0] : led2 off ( default ) [1] : led2 on d0 : led1on led1 enable control [0] : led1 off ( default ) [1] : led1 on d0 1 off 0 0 on (slope mode) on (constant current mode) off led1 operation mode 0 1 led1on led1md 1 1 0 d4 led1 operation mode this mode applies to led2, led3 operation modes, too. operation (continued) 3 register map details (continued) d o c n o . t a4 - ea - 06119 r e v i sio n . 2 e s t a b li s h e d : 2012 - 09 - 18 r e v i s e d : 2013 - 02 - 09
AN30259C product standards page 17 of 33 clkdir 40 h r / w mode address 0 0 0 0 0 0 1 0 r/w default ioen dlysel1 dlysel3 dlysel2 extpwm imax [1:0] 02 h d5 d6 d7 sel register name d0 d1 d2 d3 d4 d7-6 : imax [1:0] maximum value, step value setting for current setting [00] : maximum value 12.75 ma, step value 0.05 ma [01] : maximum value 25.50 ma, step value 0.10 ma ( default ) [10] : maximum value 31.875 ma, step value 0.125 ma [11] : maximum value 63.75 ma, step value 0.25 ma d5 : ioen clkpwm pin enable control [0] : clkpwm pin invalid ( default ) [1] : clkpwm pin valid d4 : clkdir clkpwm pin i/o mode setting [0] : clkpwm pin input mode ( default ) [1] : clkpwm pin output mode d3 : extpwm clkpwm pin pwm mode setting [0] : clkpwm pin pwm mode invalid ( default ) [1] : clkpwm pin pwm mode valid d2 : dlysel3 lighting delay time mode setting at led3 slope mode [0] : led3 delay time max 7.50 s mode ( default ) [1] : led3 delay time max 1.86 s mode d1 : dlysel2 lighting delay time mode setting at led2 slope mode [0] : led2 delay time max 7.50 s mode ( default ) [1] : led2 delay time max 1.86 s mode d0 : dlysel1 lighting delay time mode setting at led1 slope mode [0] : led1 delay time max 7.50 s mode ( default ) [1] : led1 delay time max 1.86 s mode please refer to the detail explanation of following register delay1 for dlysel* details. d4 d3 00 off 0 or 1 0 or 1 0 internal clock output mode external clock input mode external pwm operation mode clkpwm operation mode (clock mode/pwm mode) 1 0 or 1 1 extpwm clkdir ioen 0 1 1 1 d5 led lighting turns on/off by high/low setting of clkpwm pin at the time of led lighting setting. this mode enables led lighting synchronization with music signal and brightness control by high/low duty ratio. the reference clock for slope control is clkpwm pin. synchronization with external signals is possible. internal reference clock for slope control is generated via clkpwm pin. (the output clock will not be available when led1on=led2on=led3on=0.) synchronized operation can be possible when more than two pieces of this lsi are connected. operation (continued) 3 register map details (continued) d o c n o . t a4 - ea - 06119 r e v i sio n . 2 e s t a b li s h e d : 2012 - 09 - 18 r e v i s e d : 2013 - 02 - 09
AN30259C product standards page 18 of 33 00 h r / w mode address 0 0 0 0 0 0 0 0 r/w default led1cc [7 : 0] 03 h d5 d6 d7 led1cc register name d0 d1 d2 d3 d4 d7-0 : led1cc [7: 0] current setting for led1 constant current output 0.500 ma 0.250 ma 0.200 ma 0.100 ma 0 1 0 0 0 0 0 0 : 0.250 ma step : : 0.125 ma step : : 0.100 ma step : : 0.050 ma step : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 11h 10h 01h 00h 25.500 ma 25.400 ma 0.100 ma 0.000 ma 12.750 ma 12.700 ma 0.050 ma 0.000 ma imax [1 : 0] 63.750 ma 63.500 ma 0.250 ma 0.000 ma 1 1 0 0 d4 1 1 0 0 d5 1 1 0 0 d6 1 1 0 0 d2 1 1 0 0 d1 10 0.000 ma 0 0 0 31.875 ma 31.750 ma 0.125 ma 1 0 0 d0 d3 d7 1 1 1 1 led*cc [7 : 0] 00 h r / w mode address 0 0 0 0 0 0 0 0 r/w default led2cc [7 : 0] 04 h d5 d6 d7 led2cc register name d0 d1 d2 d3 d4 d7-0 : led2cc [7: 0] current setting for led2 constant current output 00 h r / w mode address 0 0 0 0 0 0 0 0 r/w default led3cc [7 : 0] 05 h d5 d6 d7 led3cc register name d0 d1 d2 d3 d4 d7-0 : led3cc [7 : 0] current setting for led3 constant current output output current value can be changed by imax setting as below. operation (continued) 3 register map details (continued) d o c n o . t a4 - ea - 06119 r e v i sio n . 2 e s t a b li s h e d : 2012 - 09 - 18 r e v i s e d : 2013 - 02 - 09
AN30259C product standards page 19 of 33 slp1tt1 [3 : 0] 88 h r / w mode address 0 0 0 1 0 0 0 1 r/w default slp1tt2 [3 : 0] 06 h d5 d6 d7 led1slp register name d0 d1 d2 d3 d4 total time of slope operation for led1 will be set. please refer to following "4. led control slope li ghting mode" for the details of slope operation. ( pwm cycle = 53.3 ? s) ? 75 ? 125 ? 12 = 6.0 s 0 0 1 1 ( pwm cycle = 53.3 ? s) ? 75 ? 125 ? 13 = 6.5 s 1 0 1 1 ( pwm cycle = 53.3 ? s) ? 75 ? 125 ? 14 = 7.0 s 0 1 1 1 : 0.5 s step : : : : : : : : : : : : : ( pwm cycle = 53.3 ? s) ? 75 ? 125 ? 2=1.0s 0 1 0 0 ( pwm cycle = 53.3 ? s) ? 75 ? 125 ? 1=0.5s 1 0 0 0 ( pwm cycle = 53.3 ? s) ? 75 ? 125 ? 15 = 7.5 s ( pwm cycle = 53.3 ? s) ? 75 ? 125 ? 0 = 0.0 s total time of slope operation 3, 4 0 0 0 0 1 1 1 1 slp1tt2 [3:0] slp1tt2 [3: 0] is set as the chart below shows. ( pwm cycle = 53.3 ? s) ? 75 ? 125 ? 12 = 6.0 s 0 0 1 1 ( pwm cycle = 53.3 ? s) ? 75 ? 125 ? 13 = 6.5 s 1 0 1 1 ( pwm cycle = 53.3 ? s) ? 75 ? 125 ? 14 = 7.0 s 0 1 1 1 : 0.5 s step : : : : : : : : : : : : : ( pwm cycle = 53.3 ? s) ? 75 ? 125 ? 2=1.0s 0 1 0 0 ( pwm cycle = 53.3 ? s) ? 75 ? 125 ? 1=0.5s 1 0 0 0 ( pwm cycle = 53.3 ? s) ? 75 ? 125 ? 15 = 7.5 s ( pwm cycle = 53.3 ? s) ? 75 ? 125 ? 0 = 0.0 s total time of slope operation 1, 2 0 0 0 0 1 1 1 1 slp1tt1 [3:0] slp1tt1 [3 : 0] is set as the chart below shows. operation (continued) 3 register map details (continued) d o c n o . t a4 - ea - 06119 r e v i sio n . 2 e s t a b li s h e d : 2012 - 09 - 18 r e v i s e d : 2013 - 02 - 09
AN30259C product standards page 20 of 33 slp2tt1 [3 : 0] 88 h r / w mode address 0 0 0 1 0 0 0 1 r/w default slp2tt2 [3 : 0] 07 h d5 d6 d7 led2slp register name d0 d1 d2 d3 d4 total time of slope operation for led2 will be set. slp3tt1 [3 : 0] 88 h r / w mode address 0 0 0 1 0 0 0 1 r/w default slp3tt2 [3 : 0] 08 h d5 d6 d7 led3slp register name d0 d1 d2 d3 d4 total time of slope operation for led3 will be set. please refer to following ? 4. led control slope lighting mode ? for the details of slope operation. the slope setting charts for led2 and led3 are the same as the one for led1 in the previous page. operation (continued) 3 register map details (continued) d o c n o . t a4 - ea - 06119 r e v i sio n . 2 e s t a b li s h e d : 2012 - 09 - 18 r e v i s e d : 2013 - 02 - 09
AN30259C product standards page 21 of 33 dutymid1 [3 : 0] f8 h r / w mode address 0 0 0 1 1 1 1 1 r/w default dutymax1 [3 : 0] 09 h d5 d6 d7 led1cnt1 register name d0 d1 d2 d3 d4 dutymin1 [3 : 0] 00 h r / w mode address 0 0 0 0 0 0 0 0 r/w default delay1 [3 : 0] 0a h d5 d6 d7 led1cnt2 register name d0 d1 d2 d3 d4 slp1dt1 [3 : 0] 88 h r / w mode address 0 0 0 1 0 0 0 1 r/w default slp1dt2 [3 : 0] 0b h d5 d6 d7 led1cnt3 register name d0 d1 d2 d3 d4 slp1dt3 [3 : 0] 88 h r / w mode address 0 0 0 1 0 0 0 1 r/w default slp1dt4 [3 : 0] 0c h d5 d6 d7 led1cnt4 register name d0 d1 d2 d3 d4 operation parameter of led1 slope operation will be set. please refer to following ? 4. led control slope lighting mode ? for the details of slope operation. d7-4 : dutymax1 [3 : 0] led1 at slope lighting maximum pwm duty setting d3-0 : dutymid1 [3 : 0] led1 at slope lighting middle pwm duty setting d7-4 : delay1 [3 : 0] led1 starting delay time setting d3-0 : dutymin1 [3 : 0] led1 at slope lighting minimum pwm duty setting d7-4 : slp1dt2 [3 : 0] led1 slope lighti ng, the period of slope operation 2 time d3-0 : slp1dt1 [3 : 0] led1 slope lighti ng, the period of slope operation 1 time d7-4 : slp1dt4 [3 : 0] led1 slope lighting, the period of slope operation 4 time d3-0 : slp1dt3 [3 : 0] led1 slope lighting, the period of slope operation 3 time operation (continued) 3 register map details (continued) d o c n o . t a4 - ea - 06119 r e v i sio n . 2 e s t a b li s h e d : 2012 - 09 - 18 r e v i s e d : 2013 - 02 - 09
AN30259C product standards page 22 of 33 duty setting for pwm operation [6 : 0] [0000111] : 7 / 128 = 5.47 % [0001111] : 15 / 128 = 11.72 % [0010111] : 23 / 128 = 17.97 % [0011111] : 31 / 128 = 24.22 % : [1110111] : 119 / 128 = 92.97 % [1111111] : 127 / 128 = 99.22 % 1 1 1 0 1 1 1 0 1 1 1 1 1 1 0 1 0 0 0 1 0 0 1 1 1 1 0 0 0 1 0 0 0 1 1 1 0 0 0 0 0 0 0 0 1 0 d5 1 ~ 0 d6 duty setting for pwm operation [6 : 0] 1 1 1 1 1 1 1 0 0 d0 d1 d2 d3 d4 d0 d1 d2 d3 1 1 1 11 111 1 ~ dutymax1 [3 : 0] dutymax1 [3 : 0] correspond to the following pwm duty setting as the following chart shows. duty setting for pwm operation [6 : 0] [0000000] : 0 / 128 = 0 % [0001111] : 15 / 128 = 11.72 % [0010111] : 23 / 128 = 17.97 % [0011111] : 31 / 128 = 24.22 % : [1110111] : 119 / 128 = 92.97 % [1111111] : 127 / 128 = 99.22 % 1 1 1 0 1 1 1 0 1 1 1 1 1 1 0 1 0 0 0 1 0 0 1 1 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 d5 1 ~ 0 d6 duty setting for pwm operation[6 : 0] 1 1 1 1 1 1 1 0 0 d0 d1 d2 d3 d4 d0 d1 d2 d3 1 1 1 11 111 1 ~ dutymid1 [3 : 0] dutymid1 [3: 0] correspond to the following pwm duty setting as the following chart shows. operation (continued) 3 register map details (continued) d o c n o . t a4 - ea - 06119 r e v i sio n . 2 e s t a b li s h e d : 2012 - 09 - 18 r e v i s e d : 2013 - 02 - 09
AN30259C product standards page 23 of 33 duty setting for pwm operation [6: 0] [0000000] : 0 / 128 = 0 % [0001000] : 8 / 128 = 6.25 % [0010000] : 16 / 128 = 12.5 % [0011000] : 24 / 128 = 18.75 % : [1110000] : 112 / 128 = 87.5 % [1111000] : 120 / 128 = 93.75 % 0 0 0 0 1 1 1 0 1 1 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 d5 1 ~ 0 d6 duty setting for pwm operation [6 : 0] 0 0 0 1 1 1 1 0 0 d0 d1 d2 d3 d4 d0 d1 d2 d3 1 1 1 10 100 1 ~ dutymin1 [3 : 0] dutymin1 [3 : 0] correspond to the following pwm duty setting as the following chart shows. 1.860 s 1.736 s ~ 0.248 s 0.124 s 0.000 s dlysel1 = 1 7.00 s 0 1 1 1 0.50 s 1 0 0 0 7.50 s ~ 1.00 s 0.00 s dlysel1 = 0 0 1 0 0 0 0 0 0 1 1 1 1 ~ delay1 [3 : 0] delay1 [3 : 0] is set as the following chart shows. operation (continued) 3 register map details (continued) d o c n o . t a4 - ea - 06119 r e v i sio n . 2 e s t a b li s h e d : 2012 - 09 - 18 r e v i s e d : 2013 - 02 - 09
AN30259C product standards page 24 of 33 ( pwm cycle = 53.3 ? s) ? 75 ? 14 = 56.0 ms 0 1 1 1 ( pwm cycle = 53.3 ? s) ? 75 ? 1 = 4.0 ms 1 0 0 0 ( pwm cycle = 53.3 ? s) ? 75 ? 15 = 60.0 ms ~ ( pwm cycle = 53.3 ? s) ? 75 ? 2 = 8.0 ms ( pwm cycle = 53.3 ? s) ? 1 = 53.3 ? s detention time at each step 0 1 0 0 0 0 0 0 1 1 1 1 ~ slp1dt1 [3 : 0] ( pwm cycle = 53.3 ? s) ? 75 ? 14 = 56.0 ms 0 1 1 1 ( pwm cycle = 53.3 ? s) ? 75 ? 1 = 4.0 ms 1 0 0 0 ( pwm cycle = 53.3 ? s) ? 75 ? 15 = 60.0 ms ~ ( pwm cycle = 53.3 ? s) ? 75 ? 2 = 8.0 ms ( pwm cycle = 53.3 ? s) ? 1 = 53.3 ? s detention time at each step 0 1 0 0 0 0 0 0 1 1 1 1 ~ slp1dt2 [3: 0] ( pwm cycle = 53.3 ? s) ? 75 ? 14 = 56.0 ms 0 1 1 1 ( pwm cycle = 53.3 ? s) ? 75 ? 1 = 4.0 ms 1 0 0 0 ( pwm cycle = 53.3 ? s) ? 75 ? 15 = 60.0 ms ~ ( pwm cycle = 53.3 ? s) ? 75 ? 2 = 8.0 ms ( pwm cycle = 53.3 ? s) ? 1 = 53.3 ? s detention time at each step 0 1 0 0 0 0 0 0 1 1 1 1 ~ slp1dt3 [3: 0] ( pwm cycle = 53.3 ? s) ? 75 ? 14 = 56.0 ms 0 1 1 1 ( pwm cycle = 53.3 ? s) ? 75 ? 1 = 4.0 ms 1 0 0 0 ( pwm cycle = 53.3 ? s) ? 75 ? 15 = 60.0 ms ~ ( pwm cycle = 53.3 ? s) ? 75 ? 2 = 8.0 ms ( pwm cycle = 53.3 ? s) ? 1 = 53.3 ? s detention time at each step 0 1 0 0 0 0 0 0 1 1 1 1 ~ slp1dt4 [3: 0] slp1dt1 [3 : 0] is set as the following chart shows. slp1dt2 [3 : 0] is set as the following chart shows. slp1dt3 [3 : 0] is set as the following chart shows. slp1dt4 [3 : 0] is set as the following chart shows. operation (continued) 3 register map details (continued) d o c n o . t a4 - ea - 06119 r e v i sio n . 2 e s t a b li s h e d : 2012 - 09 - 18 r e v i s e d : 2013 - 02 - 09
AN30259C product standards page 25 of 33 dutymid2 [3 : 0] f8 h r / w mode address 0 0 0 1 1 1 1 1 r/w default dutymax2 [3 : 0] 0d h d5 d6 d7 led2cnt1 register name d0 d1 d2 d3 d4 dutymin2 [3 : 0] 00 h r / w mode address 0 0 0 0 0 0 0 0 r/w default delay2 [3 : 0] 0e h d5 d6 d7 led2cnt2 register name d0 d1 d2 d3 d4 slp2dt1 [3 : 0] 88 h r / w mode address 0 0 0 1 0 0 0 1 r/w default slp2dt2 [3 : 0] 0f h d5 d6 d7 led2cnt3 register name d0 d1 d2 d3 d4 slp2dt3 [3 : 0] 88 h r / w mode address 0 0 0 1 0 0 0 1 r/w default slp2dt4 [3 : 0] 10 h d5 d6 d7 led2cnt4 register name d0 d1 d2 d3 d4 operation parameter of led2 slope operation will be set. each parameter is the same as led1 parameter. please refer to following ? 4. led control slope lighting mode ? for the details of slope operation. d7-4 : dutymax2 [3 : 0] led2 at slope lighting, maximum pwm duty setting d3-0 : dutymid2 [3 : 0] led2 at slope lighting, middle pwm duty setting d7-4 : delay2 [3 : 0] led2 starting delay time setting d3-0 : dutymin2 [3 : 0] led2 at slope lighting, minimum pwm duty setting d7-4 : slp2dt2 [3 : 0] led2 slope lighting, the period of slope operation 2 time d3-0 : slp2dt1 [3 : 0] led2 slope lighting, the period of slope operation 1 time d7-4 : slp2dt4 [3 : 0] led2 slope lighting, the period of slope operation 4 time d3-0 : slp2dt3 [3 : 0] led2 slope lighting, the period of slope operation 3 time operation (continued) 3 register map details (continued) d o c n o . t a4 - ea - 06119 r e v i sio n . 2 e s t a b li s h e d : 2012 - 09 - 18 r e v i s e d : 2013 - 02 - 09
AN30259C product standards page 26 of 33 dutymid3 [3 : 0] f8 h r / w mode address 0 0 0 1 1 1 1 1 r/w default dutymax3 [3 : 0] 11 h d5 d6 d7 led3cnt1 register name d0 d1 d2 d3 d4 dutymin3 [3 : 0] 00 h r / w mode address 0 0 0 0 0 0 0 0 r/w default delay3 [3 : 0] 12 h d5 d6 d7 led3cnt2 register name d0 d1 d2 d3 d4 slp3dt1 [3 : 0] 88 h r / w mode address 0 0 0 1 0 0 0 1 r/w default slp3dt2 [3 : 0] 13 h d5 d6 d7 led3cnt3 register name d0 d1 d2 d3 d4 slp3dt3 [3: 0] 88 h r / w mode address 0 0 0 1 0 0 0 1 r/w default slp3dt4 [3: 0] 14 h d5 d6 d7 led3cnt4 register name d0 d1 d2 d3 d4 d7-4 : dutymax3 [3 : 0] led3 at slope lighting maximum pwm duty setting d3-0 : dutymid3 [3 : 0] led3 at slope lighting middle pwm duty setting d7-4 : delay3 [3 : 0] led3 starting delay time setting d3-0 : dutymin3 [3 : 0] led3 at slope lighting minimum pwm duty setting d7-4 : slp3dt2 [3: 0] led3 slope light ing, the period of slope operation 2 time d3-0 : slp3dt1 [3: 0] led3 slope light ing, the period of slope operation 1 time d7-4 : slp3dt4 [3: 0] led3 slope light ing, the period of slope operation 4 time d3-0 : slp3dt3 [3: 0] led3 slope light ing, the period of slope operation 3 time operation parameter of led3 slope operation will be set. each parameter is the same as led1 parameter. please refer to following ? 4. led control slope li ghting mode ? for the details of slope operation. operation (continued) 3 register map details (continued) d o c n o . t a4 - ea - 06119 r e v i sio n . 2 e s t a b li s h e d : 2012 - 09 - 18 r e v i s e d : 2013 - 02 - 09
AN30259C product standards page 27 of 33 ? upon setting led*on to "1", constant current operation will start after the previously set starting delay time, delay*. ? as described in page 30, it is possible to turn on and o ff at high/low of clkpwm pin by making the external pwm operating mode for clkpwm pin setting valid. ? it is possible to choose "constant current lighting mode" and "slope lighting mode" by setting register led*md. to operate at "constant current mode", please set led*md at "0". ( "*" can be 1, 2, or 3.) led*on current value set by led*cc constant current operation starting delay time delay* led*md led* output current operation (continued) 4. led control constant current lighting mode d o c n o . t a4 - ea - 06119 r e v i sio n . 2 e s t a b li s h e d : 2012 - 09 - 18 r e v i s e d : 2013 - 02 - 09
AN30259C product standards page 28 of 33 ? to repeat slope operation from 1 to 4 after the previously set starting delay time, de lay*, please set register led*on at "1". ? to operate at "slope lighting mode", please set le d*md at "1". ( "*" can be 1, 2, or 3.) led*on dutymax* dutymid* dutymin* slope operation 1 slope operation 2 slope operation 3 slope operation 4 slope operation 1 slp*tt1 slp*tt2 starting delay time delay* led*md current value set at led*cc[7: 0] led*on led* output current 2.4 mhz reference clk 128 cycle duty setting 0 / 128 to 127 / 128 ? the minimum resolution of slo pe sequence control is 2.40 mhz reference clock cycle as below. slp*dt1 slp*dt2 slp*dt3 slp*dt4 slope operation 1 slope operation 2 slope operation 3 slope operation 4 operation (continued) 4. led control (continued) slope lighting mode detention time d o c n o . t a4 - ea - 06119 r e v i sio n . 2 e s t a b li s h e d : 2012 - 09 - 18 r e v i s e d : 2013 - 02 - 09
AN30259C product standards page 29 of 33 1) total time of slope operation 1, 2 total time of slope operation 1, 2 can be controlled by slp*tt1[3 : 0]. slp*tt1[3 : 0] is set as described before. ? slp*tt1[3 : 0] setting has priority to the case of slp*tt1[3 : 0] < "slope operation 1" + "slope operation 2". ? in case of that slp*tt1[3 : 0] time is over dur ing slope operation 1 (before slope operation 2), slope operation 2 is omitted and transferred to slope operation 3 from the position of dutymax. 2) total time of slope operation 3, 4 total time of slope operation 3, 4 can be controlled by slp*tt2[3: 0]. slp* tt2[3 : 0] is set as described before. ? slp*tt2[3 : 0] setting has pr iority to the case of slp*tt2[3 : 0] < "slope operation 3" + "slope operation 4". ? in case of that slp*tt2[3 : 0] time is over during slope operation 3(before slope operation 4), slope operation 4 is omitted and transferred to slo pe operation 1 from the position of dutymin. 3) dutymin, dutymid, dutymax setting for slope operation ? slope operation 1 pwm step increases step by step from the value set by dutymin*[3 : 0] to the value set by dutymid*[3 : 0]. please set the period by slp*dt1[3 : 0] for each step. the value should be dutymin*[3 : 0] < dutymid*[3 : 0]. slope operation 1 operates at dutymin = dutymid in case dutymin*[3 : 0] ? dutymid*[3 : 0] . ? slope operation 2 pwm step increases step by step from the value set by dutymid*[3 : 0] to the value set at dutymax*[3 : 0]. please set the period by slp*dt2[3 : 0] for each step. the value should be dutymid*[3 : 0] < dutymax*[3 : 0]. slope operation 2 operates at dutymid = dutymax in case dutymid*[3 : 0] ? dutymax*[3 : 0] . ? slope operation 3 pwm step decreases step by step from the value set by dutymax*[3 : 0] to the value set by dutymid*[3 : 0]. please set the period by slp*dt3[3: 0] for each step. the value should be dutymid*[3 : 0] < dutymax*[3 : 0]. slope operation 3 operates at dutymid = dutymax in case dutymid*[3 : 0] ? dutymax*[3 : 0] . ? slope operation 4 pwm step decreases step by step from the value set by du tymid*[3 : 0] to the value set by dutymin*[3 : 0]. please set the period by slp*dt4[3 : 0] for each step. the value should be dutymin*[3 : 0] < dutymid*[3 : 0]. slope operation 4 operates at dutymin = dutymid in case dutymin*[3 : 0] ? dutymid*[3: 0] . operation (continued) 4. led control (continued) d o c n o . t a4 - ea - 06119 r e v i sio n . 2 e s t a b li s h e d : 2012 - 09 - 18 r e v i s e d : 2013 - 02 - 09
AN30259C product standards page 30 of 33 4) external pwm operation mode of clkpwm pin the lighting synchronization with clkpwm signal can be turned on by setting "external pwm operation mode" in register setting. the maximum frequency which can be input to clkpwm pin is 20 khz. < at constant current mode > < at slope lighting mode> external pwm operating mode current waveform synchronized with clkpwm pin clkpwm operating mode off led*on current value set by led*cc constant current operation led* output current clkpwm (external input) external pwm operating mode current waveform synchronized with clkpwm pin clkpwm operating mode off led*on slope operation led* output current clkpwm (external input) current value set to slope setting operation (continued) 4. led control (continued) d o c n o . t a4 - ea - 06119 r e v i sio n . 2 e s t a b li s h e d : 2012 - 09 - 18 r e v i s e d : 2013 - 02 - 09
AN30259C product standards page 31 of 33 5) external clock input mode and internal clock output mode of clkpwm pin the following configuration can be made up by choosing "external clock input mode", "internal clock output mode? in register setting. vdcdc clkpwm < single application > unused state clkpwm operation off mode vdcdc clkpwm < connected application > clkpwm internal clock output mode external clock input mode ??? capable of connected operation by using synchronous clock (please refer to the explanation of the opera tion mode of p.17 for the setting of clkpwm) vdcdc < external reference clock application > clkpwm external clock input mode ??? external oscillator capable of operating using external reference clock (please refer to the explanation of the operation mode of p.17 for the setting of clkpwm) operation (continued) 4. led control (continued) d o c n o . t a4 - ea - 06119 r e v i sio n . 2 e s t a b li s h e d : 2012 - 09 - 18 r e v i s e d : 2013 - 02 - 09
AN30259C product standards page 32 of 33 package information ( reference data ) d o c n o . t a4 - ea - 06119 r e v i sio n . 2 e s t a b li s h e d : 2012 - 09 - 18 r e v i s e d : 2013 - 02 - 09
AN30259C product standards page 33 of 33 important notice 1. when using the lsi for new models, verify the safety including the long-term reliability for each product. 2. when the application system is designed by using this lsi, please confirm the notes in this book. please read the notes to descriptions and the usage notes in the book. 3. please use this product in compliance with all applicable laws and regulations that regulate the inclusion or use of control led substances, including without limitation, the eu rohs directive. our company shall not be held responsible for any damage incurred as a result of our ic being used by our customers, not complying with the applicable laws and regulations. 4. pay attention to the direction of lsi. when mounting it in the wrong direction onto the pcb (printed-circuit-board), it migh t emit smoke or ignite. 5. pay attention in the pcb (printed-circuit-board) pattern layout in order to prevent damage due to short circuit between pins . in addition, refer to the pin description for the pin configuration. 6. perform a visual inspection on the pcb before applying power, otherwise damage might happen due to problems such as a solder-bridge between the pins of the semiconductor device. also, perform a full technical verification on the assembly quality , because the same damage possibly can happen due to conductive substances, such as solder ball, that adhere to the lsi during transportation. 7. take notice in the use of this product that it might be damaged or occasionally emit smoke when an abnormal state occurs such as output pin-vcc short (power supply fault), output pin-gnd short (ground fault), or output-to-output-pin short (load short). safety measures such as an installation of fuses are recommended because the extent of the above-mentioned damage and smoke emission w ill d epend on the current capab ility of the power supply.. 8. this ic is intended to be used for general electronic equipment. consult our sales staff in advance for information on the following applications: special applications in which exceptional quality and reliab ility are required, or if the failure or malfunction of this ic may directly j eopardize life or harm the human body. any applications other than the standard applications intended. (1) space appliance (such as artificial satellite, and rocket) (2) traffic control equipment (such as for automobile, airplane, train, and ship) (3) medical equipment for life support (4) submarine transponder (5) control equipment for power plant (6) disaster prevention and security device (7) weapon (8) others : applications of which reliability equivalent to (1) to (7) is required our company shall not be held responsible for any damage incurred as a result of or in connection with the ic being used for any special application, unless our company agrees to the use of such special application. 9. this ic is neither designed nor intended for use in automotive applications or environments unless the specific product is designated by our company as compliant with the iso/ts 16949 requirements. our company shall not be held responsible for any damage incurred by customers or any third party as a result of or in connection with the ic being used in automotive application, unless our company agrees to such application in this book. 10. due to the unshielded structure of this lsi, functions and characteristics of the product cannot be guaranteed under the exposure of light. during normal operation or even under testing condition, please ensure that the lsi is not exposed to light . 11. please ensure that your design does not have metal shield parts touching the chip surface as the surface potential is gnd voltage. 12. pay attention to the breakdown voltage of this lsi when using. d o c n o . t a4 - ea - 06119 r e v i sio n . 2 e s t a b li s h e d : 2012 - 09 - 18 r e v i s e d : 2013 - 02 - 09
request for your special attention and precautions in using the technical information and semiconductors described in this book (1) if any of the products or technical information described in this book is to be exported or provided to non-residents, the laws and regulations of the exporting country, especially, those with regard to security export control, must be observed. (2) the technical information described in this book is intended only to show the main characteristics and application circuit examples of the products. no license is granted in and to any intellectual property right or other right owned by panasonic corporation or any other company. therefore, no responsibility is assumed by our company as to the infringement upon any such right owned by any other company which may arise as a result of the use of technical information described in this book. (3) the products described in this book are intended to be used for general applications (such as office equipment, communications equipment, measuring instruments and household appliances), or for specific applications as expressly stated in this book. consult our sales staff in advance for information on the following applications: ? special applications (such as for airplanes, aerospace, automotive equipment, traffic signaling equipment, combustion equipment, life support systems and safety devices) in which exceptional quality and reliability are required, or if the failure or malfunction of the products may directly jeopardize life or harm the human body. it is to be understood that our company shall not be held responsible for any damage incurred as a result of or in connection with your using the products described in this book for any special application, unless our company agrees to your using the products in this book for any special application. (4) the products and product specifications described in this book are subject to change without notice for modification and/or im- provement. at the final stage of your design, purchasing, or use of the products, therefore, ask for the most up-to-date product standards in advance to make sure that the latest specifications satisfy your requirements. (5) when designing your equipment, comply with the range of absolute maximum rating and the guaranteed operating conditions (operating power supply voltage and operating environment etc.). especially, please be careful not to exceed the range of absolute maximum rating on the transient state, such as power-on, power-off and mode-switching. otherwise, we will not be liable for any defect which may arise later in your equipment. even when the products are used within the guaranteed values, take into the consideration of incidence of break down and failure mode, possible to occur to semiconductor products. measures on the systems such as redundant design, arresting the spread of fire or preventing glitch are recommended in order to prevent physical injury, fire, social damages, for example, by using the products. (6) comply with the instructions for use in order to prevent breakdown and characteristics change due to external factors (esd, eos, thermal stress and mechanical stress) at the time of handling, mounting or at customer's process. when using products for which damp-proof packing is required, satisfy the conditions, such as shelf life and the elapsed time since first opening the packages. (7) this book may be not reprinted or reproduced whether wholly or partially, without the prior written permission of our company. 20100202

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